The present invention relates to an apparatus for producing test data to be used for detection of defects resulting during the manufacturing of a logic circuit, particularly to an apparatus for producing test data which can detect defects in a unit of a functional block of a processor LSI.
The cost of generating test data to be used for detection of defects which result during the manufacturing of logic circuit is increasing as the logic circuits become larger in scale. In order to decrease the cost of generating such test data, the test data is now produced by using an auxiliary circuit for testing. However, in many cases, it is required to operate the logic circuit at a high speed, or to decrease the area of the overall circuit as much as possible.
In the logic circuit required for high speed operation, it is very difficult to install an auxiliary circuit for testing, because the delay of a signal in the auxiliary circuit exceeds its allowable range. Further, in a circuit in which it is required to minimize the area of the circuit, there is a fear that the area of the auxiliary circuit for testing may exceed its allowable range. The extent of the difficulty of installation of the auxiliary circuit for testing and the possibility of the installation are different for every processor LSI, namely, for every functional block which is a component of the construction of the processor LSI.
While various methods are proposed in connection with the generation of test data for a logic circuit for which it is impossible to install auxiliary circuit for testing, the technique for generating in real time test data which can detect the defects which occur in manufacturing a logic circuit with high reliability has not yet been established. It is, therefore, extremely desirable to develop an actually useful method of producing test data.
An example of the prior art for producing test data in which an auxiliary circuit for testing can not be installed is disclosed on pages 28 to 37 of the paper titled "Essential: An Efficient Self-Learning Test Pattern Generation Algorithm For Sequential Circuits" by M. H. Schulz and E. Auth in "International Test Conference 1989" held in August, 1989. This paper describes an algorithm in which the test data generating problem is dealt with as a problem concerning a combination of signal values. In this regard, the combination of signal values, or the test data used to detect a fault, is searched by analyzing the logic data in a gate level with respect to the logic circuit for the test data to be made, selecting one of the circuit failures to be detected, and repeating the setting of the signal values and the cancellation of the setting of the signal values with respect to circuit terminals and inside signal lines. This processing is performed on all of the failures assumed in the logic circuit.
Further, because it is necessary to search the logic data of the whole processor LSI by using the algorithm, even when the test data for a functional block of the set processor LSI is made, the number of times the combination of signal values must be searched is extremely increased. As a result, it is very difficult to produce in real time test data which can indicate the defects in manufacturing of a logic circuit with high reliability.